IC Integrated Circuit
3D-IC Three Dimensional Integrated Circuit
SSI Small-Scale Integration
3D-IC Three Dimensional Integrated Circuit
SSI Small-Scale Integration
MSI Medium-Scale Integration
LSI Large Scale Integration
PI Physical Integration
FCI Full Chip Integration
FCFP Full Chip Floorplan
FCT Full Chip Timing
LSI Large Scale Integration
VLSI Very Large Scale Integration
ULSI Ultra Large Scale Integration
WSI Wafer Scale Integration
SoC System on Chip
ASIC Application Specific Integrated Chip
ASSP Application Specific Standard Parts
PAL Programmable Array Logic
PLD Programmable Logic Device
CPLD Complex Programmable Logic Device
FPGA Field Programmable Gate Array
NOC Network on Chip
WSI Wafer Scale Integration
SoC System on Chip
ASIC Application Specific Integrated Chip
ASSP Application Specific Standard Parts
PAL Programmable Array Logic
PLD Programmable Logic Device
CPLD Complex Programmable Logic Device
FPGA Field Programmable Gate Array
NOC Network on Chip
PD Physical Design
LD Logic Design
DFT Design For Test
JTAG Joint Test Action Group
TAP Test Access Port
BSDL Boundary Scan Description Language
AOI Automated Optical Inspection
AXI Automated X-Ray Inspection
ICT In-Circuit Test
LSSD Level-Sensitive Scan Design
SVF Serial Vector Format
JTAG Joint Test Action Group
TAP Test Access Port
BSDL Boundary Scan Description Language
AOI Automated Optical Inspection
AXI Automated X-Ray Inspection
ICT In-Circuit Test
LSSD Level-Sensitive Scan Design
SVF Serial Vector Format
PNR Place and Route
APR Advanced Place and Route
ECO Engineering Change Order
PI Physical Integration
FCI Full Chip Integration
FCFP Full Chip Floorplan
FCT Full Chip Timing
STA Static Timing Analysis
SI Signal Integrity
SI Signal Integrity
LEC Logical Equivalence Check
VCD Value Change Dump
IR Current Resistance
EM Electro Migration
PV Physical Verification
DRC Design Rule Check
LVS Layout Versus Schematic
DFM Design For Manufacturability
PM Pattern Matching
MAS Manufacturability Analysis Score
OPC Optical Proximity Correction
OATS OPC Automation Testing
LFD Litho Friendly Design
CPP Contacted Poly Pitch
MMP Minimum Metal Pitch
FIB Focused Ion Beam
DPPM Defective Parts Per Million
MMP Minimum Metal Pitch
FIB Focused Ion Beam
DPPM Defective Parts Per Million
CDRS Customer Device Requirement Spec
MEBES Manufacturing Electron Beam Exposure System
eJDV Electronic Job Deck View
EUV Extreme Ultraviolet Lithography
PCB Printed Circuit Board
MEBES Manufacturing Electron Beam Exposure System
eJDV Electronic Job Deck View
EUV Extreme Ultraviolet Lithography
PCB Printed Circuit Board
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